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M27C801
8 Mbit (1Mb x 8) UV EPROM and OTP EPROM
s
5V 10% SUPPLY VOLTAGE in READ OPERATION ACCESS TIME: 45ns LOW POWER CONSUMPTION: - Active Current 35mA at 5MHz - Standby Current 100A
1 32
s s
32
1
s s s
PROGRAMMING VOLTAGE: 12.75V 0.25V PROGRAMMING TIME: 50s/word ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 42h
FDIP32W (F)
PDIP32 (B)
DESCRIPTION The M27C801 is an 8 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for applications where fast turn-around and pattern experimentation are important requirements and is organized as 1,048,576 by 8 bits. The FDIP32W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C801 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.
PLCC32 (C)
TSOP32 (N) 8 x 20 mm
Figure 1. Logic Diagram
VCC
20 A0-A19
8 Q0-Q7
E GVPP
M27C801
VSS
AI01267
March 2000
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M27C801
Figure 2A. DIP Connections Figure 2B. PLCC Connections
A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 M27C801 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI01268
VCC A18 A17 A14 A13 A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3
A7 A6 A5 A4 A3 A2 A1 A0 Q0
A12 A15 A16 A19 VCC A18 A17 1 32 A14 A13 A8 A9 A11 GVPP A10 E Q7 9 M27C801 25 17 Q1 Q2 VSS Q3 Q4 Q5 Q6
AI01814
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A19 Q0-Q7 Address Inputs Data Outputs Chip Enable Output Enable / Program Supply Supply Voltage Ground
A11 A9 A8 A13 A14 A17 A18 VCC A19 A16 A15 A12 A7 A6 A5 A4
1
32
8 9
M27C801 (Normal)
25 24
16
17
AI01269
GVPP A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3
E GVPP VCC VSS
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M27C801
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14 Unit C C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Output Disable Program Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V 0.5V.
E V IL V IL VIL Pulse VIH VIH V IL
GVpp VIL VIH VPP VPP X VIL
A9 X X X X X V ID
Q7-Q0 Data Out Hi-Z Data In Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 1 Q5 1 0 Q4 0 0 Q3 0 0 Q2 0 0 Q1 0 1 Q0 0 0 Hex Data 20h 42h
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M27C801
Table 5. AC Measurement Conditions
High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns (10% to 90%) 0.4 to 2.4V 0.8 and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01822
1N914
3.3k
Standard 2.4V
OUT CL
0.4V
CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condition V IN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION The operating modes of the M27C801 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature and Margin Mode Set or Reset. Read Mode The M27C801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the ad-
dresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C801 has a standby mode which reduces the supply current from 35mA to 100A. The M27C801 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input.
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M27C801
Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 5V 10%)
Symbol ILI ILO ICC ICC1 ICC2 IPP V IL VIH (2) VOL VOH Output High Voltage CMOS Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL IOL = 2.1mA IOH = -1mA IOH = -100A 3.6 V CC - 0.7 Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, GVPP = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC - 0.2V VPP = VCC -0.3 2 Min Max 10 10 35 1 100 10 0.8 VCC + 1 0.4 Unit A A mA mA A A V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 5V 10%)
M27C801 Symbol Alt Parameter Test Condition -45 (3) Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE t OE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, GVPP = VIL GVPP = VIL E = VIL GVPP = VIL E = VIL E = VIL, GVPP = VIL 0 0 0 Max 45 45 25 25 25 0 0 0 Min -60 Max 60 60 30 25 25 0 0 0 Min -70 Max 70 70 35 30 30 ns ns ns ns ns ns Unit
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
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M27C801
Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 5V 10%)
M27C801 Symbol Alt Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ (2) t GHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, GVPP = VIL GVPP = VIL E = VIL GVPP = VIL E = VIL E = VIL, GVPP = VIL 0 0 0 -80 Max 80 80 40 35 35 0 0 0 -100/-120/-150 Min Max 100 100 50 40 40 ns ns ns ns ns ns Unit
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A19
VALID tAVQV tAXQX
VALID
E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ
AI01583B
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line
output control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
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M27C801
Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol ILI ICC IPP V IL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -1mA 3.6 11.5 12.5 E = VIL -0.3 2 Test Conditio n VIL VIN VIH Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Table 10. MARGIN MODE AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tA9HVPH tVPHEL tA10HEH tA10LEH tEXA10X t EXVPX tVPXA9X Alt t AS9 tVPS tAS10 tAS10 tAH10 tVPH tAH9 Parameter VA9 High to VPP High VPP High to Chip Enable Low VA10 High to Chip Enable High (Set) VA10 Low to Chip Enable High (Reset) Chip Enable Transition to VA10 Transition Chip Enable Transition to VPP Transition VPP Transition to VA9 Transition Test Condition Min 2 2 1 1 1 2 2 Max Unit s s s s s s s
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C801 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0' will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet
light (UV EPROM). The M27C801 is in the programming mode when VPP input is at 12.75V and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25V.
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M27C801
Figure 6. MARGIN MODE AC Waveforms
VCC
A8
A9 tA9HVPH GVPP tVPHEL E tA10HEH A10 Set tEXA10X tEXVPX tVPXA9X
A10 Reset tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
Table 11. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tAVEL tQVEL t VCHEL tVPHEL tVPLVPH tELEH tEHQX tEHVPX tVPLEL tELQV tEHQZ (2) t EHAX Alt tAS tDS tVCS tOES tPRT tPW tDH tOEH tVR tDV tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VCC High to Chip Enable Low VPP High to Chip Enable Low VPP Rise Time Chip Enable Program Pulse Width (Initial) Chip Enable High to Input Transition Chip Enable High to VPP Transition VPP Low to Chip Enable Low Chip Enable Low to Output Valid Chip Enable High to Output Hi-Z Chip Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 50 45 2 2 2 1 130 55 Max Unit s s s s ns s s s s s ns ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested.
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M27C801
Figure 7. Programming and Verify Modes AC Waveforms
A0-A19 tAVEL Q0-Q7 tQVEL VCC tVCHEL GVPP tVPHEL E DATA IN
VALID tEHAX DATA OUT tEHQX tEHQZ
tEHVPX
tELQV
tVPLEL
tELEH
PROGRAM
VERIFY
AI01270
Figure 8. Programming Flowchart
VCC = 6.25V, VPP = 12.75V SET MARGIN MODE
n=0
E = 50s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES RESET MARGIN MODE CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V
AI01271B
PRESTO IIB Programming Algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 52.5 seconds. This can be achieved with STMicroelectronics M27C801 due to several design innovations to improve programming efficiency and to provide adequate margin for reliability. Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 50s program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin. Program Inhibit Programming of multiple M27C801s in parallel with different data is also easily accomplished. Except for E, all like inputs including GVPP of the parallel M27C801 may be common. A TTL low level pulse applied to a M27C801's E input, with VPP at 12.75V, will program that M27C801. A high level E input inhibits the other M27C801s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at V IL. Data should be verified with tELQV after the falling edge of E.
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M27C801
On-Board Programming The M27C801 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27C801. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C801. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C801, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C801 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 A. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C801 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C801 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C801 window to prevent unintentional erasure. The recommended erasure procedure for the M27C801 is exposure to short wave ultraviolet light which has wavelength 2537 A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27C801 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
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M27C801
Table 12. Ordering Information Scheme
Example: Device Type M27 Supply Voltage C = 5V 10% Device Function 801 = 8Mbit (1Mb x8) Speed -45 (1) = 45 ns -60 = 60 ns -70 = 70 ns -80 = 80 ns -100 = 100 ns -120 = 120 ns -150 = 150 ns Package F = FDIP32W B = PDIP32 K = PLCC32 N = TSOP32: 8 x 20 mm Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Optio ns X = Additional Burn-in TR = Tape & Reel Packing M27C801 -45 K 1 TR
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 1. Revision History
Date September 1998 03/21/00 First Issue FDIP32W Package changed Revision Details
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M27C801
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
Symb A A1 A2 A3 B B1 C D D2 E E1 e eA eB L S O N 7.11 2.54 14.99 38.10 15.24 1.45 0.51 3.91 3.89 0.41 - 0.23 41.73 - - 13.06 - - 16.18 3.18 1.52 - 4 32 2.49 - 11 0.280 mm Typ Min Max 5.72 1.40 4.57 4.50 0.56 - 0.30 42.04 - - 13.36 - - 18.03 0.100 0.590 1.500 0.600 0.057 0.020 0.154 0.153 0.016 - 0.009 1.643 - - 0.514 - - 0.637 0.125 0.060 - 4 32 0.098 - 11 Typ inches Min Max 0.225 0.055 0.180 0.177 0.022 - 0.012 1.655 - - 0.526 - - 0.710
Figure 9. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2
A3 A1 B1 B D2 D S
N 1
A L eA eB C
e
E1
E
FDIPW-a
Drawing is not to scale.
12/16
M27C801
Table 14. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 15.24 38.10 15.24 1.52 mm Min - 0.38 3.56 0.38 - 0.20 41.78 - - 13.59 - - 15.24 3.18 1.78 0 32 Max 5.08 - 4.06 0.51 - 0.30 42.04 - - 13.84 - - 17.78 3.43 2.03 10 0.100 0.600 1.500 0.600 0.060 Typ inches Min - 0.015 0.140 0.015 - 0.008 1.645 - - 0.535 - - 0.600 0.125 0.070 0 32 Max 0.200 - 0.160 0.020 - 0.012 1.655 - - 0.545 - - 0.700 0.135 0.080 10
Figure 10. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale.
13/16
M27C801
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symb A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Typ Min 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ inches Min 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale.
14/16
M27C801
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm Symb Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.15 0.10 19.80 18.30 7.90 - 0.50 0 32 0.10 Min Max 1.20 0.17 1.05 0.27 0.21 20.20 18.50 8.10 - 0.70 5 0.020 0.002 0.037 0.006 0.004 0.780 0.720 0.311 - 0.020 0 32 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.319 - 0.028 5 inches
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale.
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M27C801
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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